Tesla and SpaceX Terafab: Inside the 1-TW/Year AI Chip Factory Plan

By AiCybr Editorial · Published August 8, 2026

Tesla and SpaceX are pushing their AI infrastructure strategy further upstream than buying GPUs or designing custom accelerators. Terafab is being developed as a vertically integrated semiconductor manufacturing system intended to make logic chips, high-bandwidth memory, advanced packaging and test capacity under one roof, with a long-term target of producing enough hardware for roughly 1 terawatt of compute per year.

The newest concrete milestone is the Texas production buildout. Reuters reported on August 6, 2026 that SpaceX and Tesla plan an initial $16.8 billion investment in a Terafab complex in Grimes County, Texas, with future phases potentially taking the project substantially higher. The report follows months of first-party disclosures from both companies describing Terafab’s technical scope, chip families and manufacturing model.

The important distinction is that Terafab is not simply another data center and not merely a custom-chip design program. The stated goal is to vertically integrate several semiconductor layers that are normally split across foundries, memory suppliers, packaging houses and test providers.

Terafab at a glance

The primary technical evidence comes from SpaceX’s 2026 prospectus, SpaceX’s AI infrastructure page, Tesla’s 2026 shareholder materials, and Tesla’s live Terafab engineering roles. Reuters’ August 6 report adds the current Grimes County investment and site details.

The unusual part: logic, memory and packaging in one system

Most AI-chip supply chains are highly disaggregated.

A company may design an accelerator, contract a foundry to fabricate the logic die, buy HBM from a separate memory manufacturer, rely on advanced packaging from another supplier, and use additional vendors for masks, assembly and test.

Terafab’s stated architecture compresses much more of that chain into one manufacturing program.

Tesla recruiting pages describe the facility as housing:

• logic manufacturing;
• memory manufacturing;
• advanced packaging;
• test; and
• lithography mask production.

That is unusually broad vertical integration for a company whose main businesses are vehicles, energy systems, rockets and communications rather than merchant semiconductor manufacturing.

A current Tesla lithography engineering role says Terafab engineers will work across three chip families: edge-inference processors, space-hardened chips and high-bandwidth memory. Tesla’s dry-etch role describes the same three families and explicitly references process elements including high-k dielectrics, metal gates and through-silicon vias.

Tesla’s live process-integration and dry-etch recruiting also refers to 2nm-class dimensions/process integration, including Gate-All-Around transistor architectures. That is a meaningful public engineering target, but it is not the same as a confirmed first production node, foundry process, or volume-manufacturing qualification.

Those job descriptions are useful because they reveal more about the intended manufacturing stack than the high-level corporate announcements do.

What does “1 terawatt per year of compute hardware” mean?

SpaceX’s prospectus says the Terafab initiative is intended to build manufacturing capacity capable of producing 1 terawatt per year of compute hardware.

That is a production-capacity target, not a claim that the factory itself consumes 1 TW of electrical power.

The wording describes the aggregate compute-power rating of hardware produced per year. It is therefore not directly comparable with semiconductor wafer starts, packaged accelerators per month or conventional foundry capacity figures.

The target is still remarkable because 1 TW = 1,000 GW of rated compute hardware. The actual number of chips required to reach that level would depend on the eventual device power envelopes, packaging architecture and what the companies count inside the Terafab compute portfolio.

None of those conversion assumptions has been publicly defined, so claims translating 1 TW/year into a precise annual chip count should be treated cautiously.

Why Tesla and SpaceX want their own semiconductor capacity

SpaceX’s prospectus gives a direct explanation: the companies expect future AI-chip demand to exceed the capacity they can comfortably secure from the existing industry.

The company says the objective is to extend vertical integration into chip design and manufacturing, reduce exposure to future chip shortages, optimize performance and potentially lower overall compute cost.

That motivation is broader than simply reducing purchase prices.

AI hardware availability is constrained by several linked resources:

Owning more of those layers could shorten feedback loops between chip design and manufacturing. It also creates a much harder execution problem: success depends not only on designing an accelerator but on operating an integrated semiconductor production system at competitive yield and reliability.

The first step is already separate from the large production site

Tesla’s April 2026 shareholder materials describe the Tesla-owned Research Fab at Gigafactory Texas as the beginning of the partnership with SpaceX.

That is important because the Terafab program should not be interpreted as a single factory appearing fully formed in one location.

The current public picture is better understood as a manufacturing program with multiple stages:

1. Research / process development at Tesla’s Texas research-fab operation.
2. Chip and process engineering, reflected by the growing Terafab hiring program.
3. Large-scale integrated manufacturing, including the Grimes County complex reported on August 6.

Reuters describes the planned Grimes County facility as approximately 100 million square feet, intended to make, package and test advanced logic and memory chips. SpaceX said the initial investment would be $16.8 billion and that the project would employ at least 3,000 people.

Earlier project filings contemplated substantially larger investment across additional phases. Those later phases should not be presented as already committed expenditure.

Tesla AI5 is related, but the exact Terafab production map is not public

Tesla has separately said that it completed final chip design for its next-generation AI5 inference processor in April 2026.

That establishes an important internal chip-design capability, but it does not mean every AI5 device will immediately be manufactured in Terafab.

The companies have not publicly disclosed:

• which specific AI5 revisions will be fabricated internally;
• which foundries will manufacture early or external production runs;
• which exact commercial process technology will be used for Terafab’s first logic products;
• whether Terafab’s first large-volume product will be AI5, a SpaceX processor, HBM, or another device; or
• how internal and external semiconductor capacity will be divided.

Tesla recruiting indicates 2nm-class process-development targets, but that does not establish the exact first production node, process owner, or qualification status.

The safe conclusion is narrower: Tesla is already designing advanced inference silicon, and Terafab is intended to create an internal manufacturing path for multiple future chip families.

SpaceX has a second reason for needing custom chips: orbital AI

SpaceX’s AI infrastructure strategy makes Terafab more unusual than a conventional automotive chip project.

Its STARMIND / AI1 description outlines satellites carrying localized AI compute in sun-synchronous orbit and sending results back through Starlink laser links. SpaceX lists a 150 kW peak / 120 kW average compute payload for its AI1 satellite concept and says a planned Gigasat Factory would support scaled satellite production.

SpaceX explicitly identifies AI chips as one of the limiting factors in scaling orbital compute and says the company plans to manufacture advanced AI chips through the joint Tesla fab program.

At the same time, SpaceX explicitly describes the AI1 architecture as AI-chip-vendor agnostic and says its system supports compute modules from any provider. Its prospectus also says SpaceX expects to continue sourcing a significant portion of compute hardware from third parties. Terafab is therefore intended to add internal capacity, not eliminate outside suppliers from every SpaceX AI system.

The chip families reveal the scope

The strongest technical clue about Terafab’s breadth comes from Tesla’s current hiring descriptions.

Edge-inference processors

These are the most natural fit for Tesla’s vehicle and robotics workloads, where inference must happen with tight latency, power and thermal limits.

Space-hardened chips

Space hardware has requirements that differ from normal data-center accelerators, including radiation tolerance, thermal cycling, reliability and constrained power/mass budgets. SpaceX’s planned orbital AI systems create a plausible internal consumer for this family.

High-bandwidth memory

HBM is one of the most difficult and strategic parts of current AI hardware supply. Tesla’s job descriptions explicitly identify high-bandwidth memory as a Terafab chip family rather than mentioning memory only as something purchased alongside logic.

That does not prove Tesla or SpaceX has already developed a competitive HBM product. No HBM generation, bandwidth, stack height, DRAM process or production milestone has been disclosed. It does confirm that the project intends to work directly on the memory side of the AI-compute bottleneck.

Where Intel fits

SpaceX’s prospectus describes a proposed Intel contribution to Terafab, specifically Intel expertise in designing, fabricating and packaging high-performance chips at scale.

The same SpaceX risk disclosures are important context: SpaceX says its arrangement with Tesla is a framework agreement and warns that neither Tesla nor Intel is obligated to remain part of the project, and that definitive agreements may not be entered into.

It would therefore be premature to describe Intel as a fully committed manufacturing partner, to say Terafab is replacing outside foundries, or to assume Intel has been selected for a specific production node. The confirmed point is narrower: SpaceX is planning Terafab around shared Tesla/SpaceX resources and a proposed Intel contribution while still expecting significant third-party hardware sourcing.

What remains unknown

The scale of the proposal is clear. Many of the details needed to assess its competitiveness are not.

Still undisclosed are:

• the exact first commercial production node and process owner;
• foundry/tool vendor allocation;
• first production chip;
• wafer-start capacity;
• yield targets;
• HBM generation and bandwidth;
• packaging architecture;
• reticle/die size targets;
• exact production timetable;
• first volume-production date;
• cost per packaged accelerator;
• division of manufacturing between Terafab and external suppliers; and
• how the 1-TW/year compute target is calculated across different device families.

Those are not minor gaps. They determine whether Terafab ultimately behaves like a specialized captive fab, a vertically integrated AI-system factory, or something closer to a large-scale semiconductor manufacturing platform.

What is already clear is the direction: Tesla and SpaceX are attempting to make semiconductor manufacturing itself part of their AI infrastructure stack. If the project reaches anything close to its stated scale, the strategic comparison will not be simply Tesla versus other automakers or SpaceX versus other launch companies. Terafab would put both companies directly into the logic-memory-packaging bottleneck that now shapes the economics of frontier AI.