TinyGPU v2.0: The 240K-Transistor Open-Source GPU That Now Runs on Real Silicon

By AiCybr Editorial · Published August 7, 2026

TinyGPU v2.0 has crossed the line that separates an interesting FPGA project from a real chip: the design has returned from fabrication and works on silicon.

The open-source GPU, designed by Pongsagon Vichit and fabricated through the Tiny Tapeout SKY 25b shuttle, runs at about 25 MHz, implements transformation and lighting plus rasterization in hardware, renders models with up to 1,000 triangles, supports flat shading and affine texture mapping, and uses external QSPI memory for its frame and depth buffers.

The project repository estimates roughly 240,000 transistors for the fabricated design. By modern GPU standards that number is tiny. That is precisely why the project is interesting.

TinyGPU v2.0 is not trying to compete with GeForce, Radeon or Arc. It is a compact, inspectable 3D graphics pipeline that demonstrates something more important for students, hobbyists and hardware engineers: a single developer can now design a non-trivial GPU, prototype it on an FPGA, send it through an open ASIC flow, and receive working silicon back.

The hardware is published under the Apache-2.0 license.

Navigate This Guide

• TinyGPU v2.0 at a glance
• What changed: FPGA prototype to working ASIC
• What TinyGPU v2.0 actually does
• Architecture and rendering pipeline
• Memory architecture
• Performance and display characteristics
• How the chip was fabricated
• Why Tiny Tapeout changes custom-chip development
• What TinyGPU is not
• TinyGPU v2.0 vs modern GPUs
• What developers can learn from the project
• Known limitations
• TinyGPU v3.0 roadmap
• Who should study or build on TinyGPU
• Frequently asked questions
• Final assessment
• Official sources

TinyGPU v2.0 at a Glance

The most important line in the table is status: tested successfully on real ASIC silicon. The rendering features themselves were already demonstrated during FPGA development. The new milestone is that the physical implementation behaves like the prototype rather than remaining a simulation or FPGA-only design.

What Changed: FPGA Prototype to Working ASIC

Before fabrication, TinyGPU v2.0 had already been exercised on a Digilent Basys3 FPGA board. That is a normal development path for digital hardware: implement the logic in a hardware-description language, synthesize it into an FPGA, validate the design, then move to an ASIC flow.

An FPGA prototype proves that the logic is largely correct, but it does not prove that the final physical chip will work.

ASIC fabrication introduces another class of concerns:

• physical placement and routing;
• timing closure;
• clock distribution;
• power distribution;
• design-rule compliance;
• I/O integration;
• foundry process assumptions;
• packaging and board connectivity.

A project can simulate correctly and work on an FPGA yet still fail after tapeout because of a physical-design or interface problem.

That is why the July 2026 result matters. The Tiny Tapeout project page now contains direct user feedback from the designer stating that the chip works as expected and behaves similarly to the FPGA test. The GitHub README is also explicitly headed “Tested on TinyTapeout ASIC.”

Independent reporting from Tom’s Hardware on August 3 documented the working-chip demonstration and noted that the finished SKY 25b silicon was running real-time 3D scenes.

This is therefore not simply a planned tapeout or a render of a chip layout. It is a working graphics ASIC.

What TinyGPU v2.0 Actually Does

TinyGPU is a deliberately compact fixed-function 3D graphics processor.

Its pipeline can take a model stored in external flash, transform the geometry, calculate basic lighting, remove back-facing triangles, rasterize visible triangles, perform depth handling, apply flat shading or affine texture mapping, and output the resulting image through VGA.

The project supports:

• model transformation;
• 3D lighting calculations;
• triangle rasterization;
• backface culling;
• one directional light;
• flat shading;
• affine texture mapping;
• a color double buffer;
• a depth buffer;
• interactive model rotation and zoom using a gamepad.

The design is closer conceptually to an early fixed-function 3D accelerator than to a modern programmable GPU.

That makes it easier to study.

A current desktop GPU combines thousands of compute units, massive cache hierarchies, programmable shader cores, hardware schedulers, ray-tracing units, matrix accelerators, video engines, display engines, memory controllers, high-speed interconnects and an enormous software stack.

TinyGPU reduces the problem to the core stages required to make a 3D object appear on a screen.

Architecture and Rendering Pipeline

A simplified TinyGPU workflow looks like this:

Model in flash → transformation → lighting → backface culling → rasterization → depth test → shading / texture mapping → frame buffer → VGA output

1. Model data

The project includes an OBJ conversion utility. A conventional .obj model can be converted into the binary representation expected by TinyGPU and stored in external QSPI flash.

This is useful because the ASIC does not need a large on-chip storage block for arbitrary 3D assets.

2. Transformation

3D vertices need to be moved from model coordinates into the coordinate system required for display.

TinyGPU performs the transformation step in hardware rather than asking a host PC to submit already-transformed screen-space triangles.

That distinction is important: this is not simply a VGA rasterizer receiving finished pixels or 2D shapes.

3. Lighting

The design supports one dynamic directional light.

The lighting model is intentionally simple, but it allows geometry orientation to affect brightness and makes the rendered object visibly three-dimensional.

4. Backface culling

Triangles facing away from the camera do not normally need to be rasterized.

Backface culling removes this unnecessary work before it reaches later stages of the pipeline.

5. Rasterization

The rasterizer converts triangle geometry into screen pixels.

This is one of the defining jobs of a traditional GPU, and TinyGPU implements it directly in hardware.

6. Depth handling

The project uses an 8-bit depth buffer stored in external QSPI RAM.

That gives the renderer a way to determine which surface should remain visible when multiple triangles cover the same pixel.

7. Shading and texturing

TinyGPU supports flat shading and affine texture mapping.

Affine texture mapping is considerably simpler than the perspective-correct interpolation used by later 3D hardware. It can visibly distort textures on surfaces viewed at steep perspective angles, but its lower complexity makes sense for an educational ASIC with a very small logic budget.

Memory Architecture

One of the most instructive parts of TinyGPU v2.0 is what isn’t stored on the chip.

The renderer uses external QSPI memory for:

• the 4-bit double frame buffer;
• the 8-bit depth buffer;
• model and texture data.

This architectural choice saves a large amount of silicon area.

Why external memory matters

At 320×240 resolution, even apparently tiny buffers become significant compared with the logic budget of a Tiny Tapeout design.

A single 4-bit 320×240 image contains:

320 × 240 × 4 = 307,200 bits, or about 38.4 KB before additional overhead.

A double buffer requires roughly twice that storage.

An 8-bit depth buffer at the same resolution requires another:

320 × 240 × 8 = 614,400 bits, or about 76.8 KB.

For a small educational ASIC, dedicating enough on-chip SRAM or standard-cell memory to those buffers would dominate the project.

External QSPI therefore trades bandwidth and latency for dramatically lower on-chip area.

That is an authentic hardware-design tradeoff rather than merely a workaround.

Performance and Display Characteristics

Tiny Tapeout lists the design clock at 25.175 MHz, while the project documentation generally describes it as a 25 MHz design.

The official Tiny Tapeout project page states a baseline of approximately 6.5 FPS for a 1,000-triangle model at 320×240 and 4-bit color.

Tom’s Hardware reports that different FPGA demonstrations had previously landed around 7.5–15 FPS, depending on the workload, and that the ASIC was not expected to become materially faster simply because it had moved from FPGA to fabricated silicon.

Those numbers should not be treated as a standardized graphics benchmark. Different models, triangle counts and scene characteristics change the amount of work per frame.

The important observation is simpler:

TinyGPU can render and interact with non-trivial 3D models in real time on a physically fabricated, extremely small open-source graphics ASIC.

Why 320×240 and 4-bit color?

Because every extra pixel and every extra bit of color or depth increases bandwidth and storage requirements.

TinyGPU is optimized for design clarity and fit rather than image quality.

A low-resolution render target allows the project to demonstrate the entire 3D pipeline without turning the memory subsystem into the whole chip.

How the Chip Was Fabricated

TinyGPU v2.0 was included in the Tiny Tapeout SKY 25b shuttle.

Tiny Tapeout says the shuttle:

• launched on September 18, 2025;
• closed submissions on November 10, 2025;
• was submitted to the ChipFoundry CI2511 shuttle;
• used the SkyWater 130 nm open-source PDK;
• was expected back in July 2026.

The TinyGPU block appears as project 70 on the SKY 25b chip.

What is a shuttle?

Fabricating an entire wafer for one small experimental design would be prohibitively expensive for most individuals.

A shuttle combines many unrelated designs into one manufacturing run. Each participant receives only a small region of the final chip or wafer area.

Tiny Tapeout adds another abstraction layer on top of this multi-project-wafer model. It standardizes the project interface and physical slots so hundreds of small digital and analog projects can share a fabrication run.

SKY 25b contained 316 submitted designs, according to Tiny Tapeout.

TinyGPU therefore did not require its designer to fund a dedicated production mask set and wafer run.

Why Tiny Tapeout Changes Custom-Chip Development

The deeper story is not that somebody created a very small GPU.

The deeper story is that custom ASIC development is becoming dramatically more accessible.

Historically, learning digital design could stop at simulation or an FPGA because real fabrication required specialized flows, foundry relationships and substantial money.

Open silicon projects now combine:

• open-source process design kits;
• open HDL designs;
• automated synthesis and physical-design tools;
• shared fabrication shuttles;
• standardized development boards;
• continuous integration for chip builds;
• public repositories and reproducible examples.

The TinyGPU repository notes that its GitHub workflow can automatically build ASIC files through the Tiny Tapeout flow using LibreLane.

That means a learner can study much more than Verilog syntax. They can examine the entire path from RTL to physical silicon.

The educational progression now looks like this

TinyGPU v2.0 spans that complete chain.

What TinyGPU Is Not

Calling TinyGPU a GPU does not mean it belongs in the same product category as a GeForce RTX, Radeon RX or Intel Arc graphics card.

It lacks nearly every subsystem expected from a modern GPU.

TinyGPU v2.0 does not provide:

• programmable vertex shaders;
• programmable pixel shaders;
• general-purpose compute kernels;
• CUDA, ROCm, OpenCL or Vulkan compute support;
• hardware ray tracing;
• tensor/matrix accelerators;
• high-bandwidth local VRAM;
• modern texture filtering;
• sophisticated compression;
• large caches;
• multi-display controllers;
• PCI Express integration;
• a production desktop graphics driver stack.

It is better understood as a compact fixed-function graphics pipeline implemented as an ASIC.

That is not a criticism. Removing those systems is what makes the design small enough to understand and fabricate through a platform such as Tiny Tapeout.

TinyGPU v2.0 vs Modern GPUs

A direct benchmark comparison would be meaningless, but an architectural comparison is useful.

The transistor-scale row should be read as an order-of-magnitude illustration rather than a performance metric. Modern GPUs use their enormous budgets for features TinyGPU intentionally omits.

What Developers Can Learn From the Project

TinyGPU is unusually useful because the repository exposes the implementation rather than only describing an architecture in a paper.

GPU pipeline design

Developers can follow how geometry becomes pixels without first understanding the huge software and hardware stack of a commercial GPU.

Fixed-point arithmetic

Small ASICs often avoid expensive floating-point units. Graphics is a useful environment for learning how fixed-point representation affects precision, range and hardware area.

Bandwidth versus area tradeoffs

Moving frame and depth storage to QSPI memory reduces silicon area but constrains throughput.

That is the same class of tradeoff—at a radically different scale—that professional accelerator designers make when balancing on-chip SRAM, cache, HBM and external memory traffic.

FPGA-to-ASIC differences

Because the same design was prototyped on Basys3 and then fabricated, the repository provides a useful reference for developers who want to move beyond FPGA-only projects.

Verification

A graphics pipeline produces a visible result. Incorrect transforms, rasterization bugs, depth problems and texture errors can often be identified immediately on screen.

That makes graphics hardware particularly rewarding for education.

Known Limitations

The repository currently documents one especially important rendering limitation:

A model cannot be rendered beyond the viewport; doing so can freeze the GPU and require a reset.

The author says this issue is addressed in the planned v3.0 design.

Other practical constraints follow directly from the architecture:

• limited QSPI bandwidth;
• low clock rate;
• very small triangle budget by modern standards;
• low resolution;
• 4-bit color;
• low-precision depth;
• affine rather than perspective-correct texturing;
• no programmable shader stage.

These are architectural boundaries, not defects in the project concept.

The goal is a functioning, understandable GPU pipeline that fits within an extremely small ASIC allocation.

TinyGPU v3.0 Roadmap

TinyGPU v3.0 has been announced by the designer but should be treated as a roadmap, not a shipping product.

Tom’s Hardware reported that Vichit plans a v3.0 revision for around the end of 2026. Reported goals include approximately 290,000 transistors and new features such as:

• a programmable pixel shader;
• improved clipping;
• better interaction with the Z-buffer;
• fixes for the viewport limitation.

Until the RTL is finalized and silicon is fabricated, those details remain development targets rather than validated hardware specifications.

That distinction is important because the most notable achievement of v2.0 is exactly what v3.0 has not yet demonstrated: working fabricated silicon.

Who Should Study or Build on TinyGPU

FPGA developers

If you already understand RTL and have implemented CPUs, VGA controllers or accelerators, TinyGPU is a useful next step into a complete 3D pipeline.

Computer-architecture students

The project turns textbook stages such as transformation, culling, rasterization and buffering into inspectable hardware.

GPU programmers

Developers who normally work at the Vulkan, Direct3D, OpenGL or CUDA level can use a project like this to understand what sits beneath the API abstraction.

Open-silicon contributors

TinyGPU demonstrates how much can fit inside the constraints of a shared open ASIC shuttle.

Makers considering their first tapeout

The project is valuable not because a first-time designer should immediately copy a GPU, but because it shows that surprisingly sophisticated digital systems can now move through accessible fabrication workflows.

Frequently Asked Questions

Is TinyGPU v2.0 really a physical chip?

Yes. The project repository explicitly states that it has been tested on the Tiny Tapeout ASIC, the Tiny Tapeout project page records successful user feedback from the designer, and independent reporting published a working-silicon demonstration.

Is it the world’s smallest GPU?

The project and media coverage describe it as the “tiniest” or “world’s smallest” GPU, but there is no universal standards body that certifies that title. The safer technical claim is that it is an unusually small standalone 3D graphics ASIC with an estimated ~240,000 transistors.

How many triangles can it render?

The project specifies models of up to 1,000 triangles.

What resolution does it target?

The documented baseline is 320×240 with 4-bit color.

What frame rate does it achieve?

Tiny Tapeout documents about 6.5 FPS for a 1,000-triangle example. Independent reporting cites prior FPGA demonstrations around 7.5–15 FPS depending on workload. These are demonstration results, not a standardized benchmark suite.

What process node is it built on?

The SKY 25b shuttle used the SkyWater 130 nm open-source PDK through ChipFoundry CI2511.

Is TinyGPU open source?

Yes. The GitHub repository publishes the project under the Apache-2.0 license.

Can it run modern PC games?

No. It lacks the programmable shader architecture, memory bandwidth, APIs, driver stack and performance required for modern games.

Can I study the RTL?

Yes. The source repository includes the hardware project, ASIC flow files, FPGA prototype material, model conversion code, documentation and tests.

Why is this important if it is so slow?

Because the milestone is accessibility, not performance. TinyGPU shows that an individual can design, prototype and fabricate a real GPU-like ASIC using open tools and shared fabrication infrastructure.

Final Assessment

TinyGPU v2.0 is interesting for the opposite reason modern GPUs are interesting.

NVIDIA, AMD and Intel demonstrate what happens when enormous transistor budgets, advanced process nodes and massive engineering teams are applied to graphics and compute.

TinyGPU demonstrates how little hardware is required to reconstruct the essential ideas of a 3D graphics pipeline—and how accessible real silicon has become to individual developers.

The key achievement is not 6.5 FPS, 320×240 output or 1,000 triangles.

It is the complete path:

open RTL → FPGA prototype → automated ASIC flow → shared shuttle → fabricated 130 nm silicon → working 3D graphics.

For open-hardware developers, students and anyone interested in how GPUs actually work beneath modern APIs, that makes TinyGPU v2.0 far more useful than its raw performance numbers suggest.

Official Sources

Primary sources

• TinyGPU v2.0 GitHub repository — source code, architecture, ASIC/FPGA test status and Apache-2.0 license: https://github.com/pongsagon/tt_um_pongsagon_tinygpu_v2
• Tiny Tapeout — Tiniest GPU V2 project page and validated SKY 25b project details: https://tinytapeout.com/chips/ttsky25b/tt_um_pongsagon_tinygpu_v2
• Tiny Tapeout SKY 25b shuttle — SkyWater 130 nm PDK, ChipFoundry CI2511 shuttle and project list: https://tinytapeout.com/chips/ttsky25b/

Independent reporting

• Tom’s Hardware — World’s smallest GPU silicon passes real-world testing, August 3, 2026: https://www.tomshardware.com/pc-components/gpus/worlds-smallest-gpu-silicon-passes-real-world-testing-240-000-transistor-tinygpu-v2-0-renders-3d-graphics-at-up-to-15-fps-while-v3-0-prepares-for-2026-release

Validation note: Specifications in this guide were checked on August 7, 2026 against the current TinyGPU repository, the Tiny Tapeout SKY 25b project records and independent reporting. TinyGPU v3.0 details are roadmap claims and are explicitly labeled as such.